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| INTEGRATED CIRCUITS PCA9518 Expandable 5-channel I2C hub Product data 2002 Aug 20 Philips Semiconductors Philips Semiconductors Product data Expandable 5-channel I2C hub PCA9518 PIN CONFIGURATION EXPSCL1 EXPSCL2 SCL0 1 2 3 4 5 6 7 8 9 20 VCC 19 EXPSDA2 18 EXPSDA1 17 EN4 16 SDA4 15 SCL4 14 EN3 13 SDA3 12 SCL3 11 EN2 DESCRIPTION The PCA9518 is a BiCMOS integrated circuit intended for application in I2C and SMBus systems. While retaining all the operating modes and features of the system, it permits extension of the I2C-bus by buffering both the data (SDA) and the clock (SCL) lines, thus enabling virtually unlimited buses of 400 pF. The I2C-bus capacitance limit of 400 pF restricts the number of devices and bus length. Using the PCA9518 enables the system designer to divide the bus into an unlimited number of segments off of a hub where any segment to segment transition sees only one repeater delay and is multiple master capable on each segment. Using multiple PCA9518 parts, any width hub (in multiples of five)1 can be implemented using the expansion pins. I2C SDA0 SCL1 SDA1 EN1 SCL2 SDA2 GND 10 SU01595 Figure 1. Pin configuration PIN DESCRIPTION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 SYMBOL EXPSCL1 EXPSCL2 SCL0 SDA0 SCL1 SDA1 EN1 SCL2 SDA2 GND EN2 SCL3 SDA3 EN3 SCL4 SDA4 EN4 EXPSDA1 EXPSDA2 VCC FUNCTION Expandable serial clock pin 1 Expandable serial clock pin 2 Serial clock bus 0 Serial data bus 0 Serial clock bus 1 Serial data bus 1 Active High Bus 1 enable Input Serial clock bus 2 Serial data bus 2 Supply ground Active High Bus 2 enable Input Serial clock bus 3 Serial data bus 3 Active High Bus 3 enable Input Serial clock bus 4 Serial data bus 4 Active High Bus 4 enable Input Expandable serial data pin 1 Expandable serial data pin 2 Supply power FEATURES * Expandable 5 channel, bi-directional buffer * I2C-bus and SMBus compatible * Active high individual repeater enable inputs * Open-drain input/outputs * Lock-up free operation * Supports arbitration and clock stretching across the repeater * Accommodates standard mode and fast mode I2C devices and * Powered-off high impedance I2C pins * Operating supply voltage range of 3.0 V to 3.6 V * 5 V tolerant I2C and enable pins * 0 to 400 kHz clock frequency2 * ESD protection exceeds 2000 V HBM per JESD22-A114, * Latch-up testing is done to JEDEC Standard JESD78 which * Package offerings: SO and TSSOP ORDERING INFORMATION PACKAGES 20-pin plastic SO 20-pin plastic TSSOP TEMPERATURE RANGE -40 to +85 C -40 to +85 C exceeds 100 mA. 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101. multiple masters ORDER CODE PCA9518D PCA9518PW TOPSIDE MARK PCA9518D PCA9518 DRAWING NUMBER SOT163-1 SOT360-1 Standard packing quantities and other packaging data is available at www.philipslogic.com/packaging. 1. 2. Only four ports per device are available if individual Enable is required. The maximum system operating frequency may be less than 400 KHz because of the delays added by the repeater. 2002 Aug 20 2 853-2364 28791 Philips Semiconductors Product data Expandable 5-channel I2C hub PCA9518 VCC PCA9518 EXPSCL1 EXPSCL2 SCL0 Buffer Buffer Hub Logic Buffer SCL3 SCL4 SCL1 Buffer SCL2 Buffer EXPSDA1 EXPSDA2 SDA0 Buffer Buffer Hub Logic Buffer SDA3 SDA4 SDA1 Buffer SDA2 Buffer EN1 EN4 EN2 EN3 GND SU01596 Figure 2. Block Diagram: PCA9518 A more detailed view of Figure 2 buffer is shown in Figure 3. The output pull-down voltage of each internal buffer is set for approximately 0.5 V, while the input threshold of each internal buffer is set about 0.07 V lower, when the output is internally driven low. This prevents a lock-up condition from occurring. To output Data z In Inc Enable SW00712 Figure 3. 2002 Aug 20 3 Philips Semiconductors Product data Expandable 5-channel I2C hub PCA9518 FUNCTIONAL DESCRIPTION The PCA9518 BiCMOS integrated circuit is a five way hub repeater, which enables I2C and similar bus systems to be expanded in increments of five with only one repeater delay and no functional degradation of system performance. The PCA9518 BiCMOS integrated circuit contains five multi-directional, open drain buffers specifically designed to support the standard low-level-contention arbitration of the I2C-bus. Except during arbitration or clock stretching, the PCA9518 acts like a pair of non-inverting, open drain buffers, one for SDA and one for SCL. connected to a 3.3 V or 5 V bus. All buses run at 100 kHz unless slave 3, 4 and 5 are isolated from the bus. Then the master bus and slave 1, 2 and 6 can run at 400 kHz. Any segment of the hub can talk to any other segment of the hub. Bus masters and slaves can be located on any segment with 400 pF load allowed on each segment. The PCA9518 is 5 V tolerant so it does not require any additional circuitry to translate between the different bus voltages. When one port of the PCA9518 is pulled low by a device on the I2C bus, a CMOS hysteresis type input detects the falling edge and drives the EXPXXX1 line low, when the EXPXXX1 voltage is less than1/2VCC, the other ports are pulled down to the VOL of the PCA9518 which is typically 0.5 V. In order to illustrate what would be seen in a typical application, refer to Figure 5. If the bus master in Figure 4 were to write to the slave through the PCA9518, we would see the waveform shown in Figure 5. This looks like a normal I2C transmission except for the small foot preceding each clock low to high transition and proceeding each data low to high transition for the master. The foot height is the difference between the low level driven by the master and the higher voltage low level driven by the PCA9518 repeater. Its width corresponds to an effective clock stretching coming from the PCA9518 which delays the rising edge of the clock. That same magnitude of delay is seen on the rising edge of the data. The foot on the rising edge of the data is extended through the 9th clock pulse as the PCA9518 repeats the acknowledge from the slave to the master. The clock of the slave looks normal except the VOL is the 0.5 V level generated by the PCA9518. The SDA at the slave has a particularly interesting shape during the 9th clock cycle where the slave pulls the line below the value driven by the PCA9518 during the acknowledge and then returns to the PCA9518 level creating a foot before it completes the low to high transition. SDA lines other than the one with the master and the one with the slave have a uniform low level driven by the PCA9518 repeater. The other four waveforms are the expansion bus signals and are included primarily for timing reference points. All timing on the expansion bus is with respect to 0.5 VCC. EXPSDA1 is the expansion bus that is driven low whenever any SDA pin falls below 0.3 VCC. EXPSDA2 is the expansion bus that is driven low whenever any pin is 0.4 V. EXPSCL1 is the expansion bus that is driven low whenever any SCL pin falls below 0.3 VCC. EXPSCL2 is the expansion bus that is driven low whenever any SCL pin is 0.4 V. The EXPSDA2 returns high after the SDA pin that was the last one being held below 0.4 V by an external driver starts to rise. The last SDA to rise above 0.4 V is held down by the PCA 9518 to 0.5 V until after the delay of the circuit which determines that it was the last to rise, then it is allowed to rise above the 0.5 V level driven by the PCA9518. Considering the bus 0 SDA to be the last one to go above 0.4 V, then the EXPSDA1 returns to high after the EXPSDA2 is high and either the bus 0 SDA rise time is 1 s or, when the bus 0 SDA reaches 0.7 VCC, whichever occurs first. After both EXPSDA2 and EXPSDA1 are high the rest of the SDA lines are allowed to rise. The same description applies for the EXPSCL1, EXPSCL2, and SCL pins. Enable The enable pins EN1 through EN4 are active high and have internal pull-up resistors. Each enable pin ENn controls its associated SDAn and SCLn ports. When low, the ENn pin blocks the inputs from SDAn and SCLn, as well as disabling the output drivers on the SDAn and SCLn pins. The enable pins should only change state when both the global bus and the local port are in an idle state to prevent system failures. The active high enable pins allow the use of open drain drivers which can be wire-ORed to create a distributed enable where either centralized control signal (master) or spoke signal (submaster) can enable the channel when it is idle. Expansion The PCA9518 includes 4 open drain I/O pins used for expansion. Two expansion pins, EXPSDA1 and EXPSDA2 are used to communicate the internal state of the serial data within each hub to the other hubs. The EXPSDA1 pins of all hubs are connected together to form an open drain bus. Similarly, all EXPSDA2 pins, EXPSCL1 pins, and all EXPSCL2 pins are connected together forming a 4-wire bus between hubs. When it is necessary to be able to deselect every port, each expansion device only contributes 4 ports which can be enabled or disables because the fifth does not have an enable pin. Pull-up resistors are required on the EXPXXXX3 pins even if only one PCA9518 is used. I2C Systems As with the standard I2C system, pull-up resistors are required to provide the logic HIGH levels on the Buffered bus. (Standard open-collector or open-drain configuration of the I2C-bus). The size of these pull-up resistors depends on the system, but each side of the repeater must have a pull-up resistor. This part is designed to work with standard mode (0 to 100 kHz) and fast mode (0 to 400 kHz) I2C devices in addition to SMBus devices. Standard mode I2C devices only specify 3 mA output drive, this limits the termination current to 3 mA in a generic I2C system where standard mode devices and multiple masters are possible. Please see Application Note AN255 "I 2C & SMBus Repeaters, Hubs and Expanders" for additional information on sizing resistors. APPLICATION INFORMATION A typical application is shown in Figure 4. In this example, the system master is running on a 3.3 V I2C-bus while the slaves are 3. XXXX is SDA1, SDA2, SCL1, or SCL2 XXX is SDA or SCL 2002 Aug 20 4 Philips Semiconductors Product data Expandable 5-channel I2C hub PCA9518 3.3 V 5V 5V VDD EXPSDA1 EXPSDA2 SDA SUBSYSTEM 5 SCL 100 kHz 3.3 V SDA1 EXPSCL1 SCL1 EXPSCL2 EXPSCL2 EXPSCL1 VDD EXPSDA1 EXPSDA2 SDA1 SCL1 3.3 V SDA SUBSYSTEM 1 SCL 400 kHz SDA2 SCL2 SDA0 SCL0 SDA SCL SDA0 SCL0 5V SDA SUBSYSTEM 2 SCL 400 kHz SDA SUBSYSTEM 6 SCL 400 kHz SDA2 SCL2 PCA9518 DEVICE 2 SDA3 SCL3 BUS MASTER PCA9518 DEVICE 1 SDA3 SCL3 3.3 V EN1 SDA SUBSYSTEM 3 SCL 100 kHz DISABLED NOT CONNECTED SDA4 SCL4 EN2 EN1 EN2 EN3 EN4 GND 400 kHz SDA4 GND SCL4 SDA SUBSYSTEM 4 SCL 100 kHz EN3 EN4 SW00974 NOTE: 1. Only two of the five channels on the PCA9518 Device 2 are being used. EN3 and EN4 are connected to GND to disable channels 3 and 4. SDA0 and SCL0 must be pulled-up to VCC since there is no enable pin. Figure 4. Typical application: Multiple expandable 5-channel I2C hubs 2002 Aug 20 5 Philips Semiconductors Product data Expandable 5-channel I2C hub PCA9518 9TH CLOCK CYCLE VOL OF MASTER SCL OF MASTER BUS 0 tst SDA OF MASTER VOL OF PCA9518 9TH CLOCK CYCLE EXPSDA1 tf1 tr1 tEr1 EXPSDA2 EXPANSION BUS tf2 EXPSCL1 tr2 EXPSCL2 SCL OF SLAVE BUS 1 SDA OF SLAVE tPHL tPLH VOL OF SLAVE VOL OF PCA9518 BUS n WITH n > 1 SW01090 Figure 5. Bus waveforms It is important to note that any arbitration or clock stretching events on Bus 1 require that the VOL of the devices on Bus 1 be 70 mV below the VOL of the PCA9518 (see VOL - Vilc in the DC Characteristics section) to be recognized by the PCA9518 and then transmitted to Bus 0. 2002 Aug 20 6 Philips Semiconductors Product data Expandable 5-channel I2C hub PCA9518 ABSOLUTE MAXIMUM RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134). Voltages with respect to pin GND. LIMITS SYMBOL VCC to GND Vbus I Ptot Tstg Tamb Supply voltage range VCC Voltage range I2C-bus, SCL or SDA DC current (any pin) Power dissipation Storage temperature range Operating ambient temperature range PARAMETER MIN. -0.5 -0.5 -- -- -55 -40 MAX. +7 +7 50 300 +125 +85 UNIT V V mA mW C C DC ELECTRICAL CHARACTERISTICS VCC = 3.0 to 3.6 V; GND = 0 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VCC ICCH ICCL DC supply voltage Quiescent supply current, both channels HIGH Quiescent supply current, both channels LOW Quiescent supply current in contention VCC = 3.6 V; SDAn = SCLn = VCC VCC = 3.6 V; one SDA and one SCL = GND, other SDA and SCL open VCC = 3.6 V; SDAn = SCLn = GND 3.0 -- -- 3.3 7.5 9 3.6 10 11 V mA mA PARAMETER TEST CONDITIONS LIMITS MIN. TYP. MAX. UNIT ICCLc -- 9 11 mA Input SCL; input/output SDA VIH VIL VILc VIK II IIL VOL VOL-VILc CI Enable 1-4 VIL VIH IIL ILI CI LOW level input voltage HIGH level input voltage Input current LOW Input leakage current Input capacitance VI = 3.0 V or 0 V VI = 0.2 V, EN1-EN4 -0.5 2.0 -- -1 -- 0.55 VCC -0.5 VI = 0.2 V, EXP* IOL = 12 mA VI = 3.0 V or 0 V -- -- -- -- -- 10 -- 3 0.8 5.5 30 1 7 V V A A pF High-level input voltage, SCL, SDA Low-level input voltage, SCL, SDA (Note 1) Low-level input voltage contention, SCL, SDA (Note 1) Input clamp voltage Input leakage current Input current LOW, SDA, SCL Low level output, SCL, SDA Low level input voltage below output low level voltage Input capacitance II = -18 mA VI = 3.6 V VI = 0.2 V, SDA, SCL IOL = 02 or 6 mA Guaranteed by design VI = 3 V or 0 V 0.7 VCC -0.5 -0.5 -- -- -- 0.47 -- -- -- -- -- -- -- -- 0.52 -- 6 5.5 0.3 VCC 0.4 -1.2 1 5 0.6 70 8 V V V V A A V mV pF Expansion Pins VIH VIL IIL VOL CI HIGH level input voltage, EXP* LOW level input voltage, EXP* Input current LOW, EXP* Low level output, EXP* Input capacitance -- -- -- -- 6 5.5 0.45 VCC 5 0.5 8 V V A V pF NOTE: 1. VIL specification is for the enable input and the first low level seen by the SDAx/SCLx lines. VILc is for the second and subsequent low levels seen by the SDAx/SCLx lines 2. Test performed with IOL = 10 A 2002 Aug 20 7 Philips Semiconductors Product data Expandable 5-channel I2C hub PCA9518 AC ELECTRICAL CHARACTERISTICS1 SYMBOL tPHLs tPLHs tPHLE1s tPLHE1s tPLHE2s tTHLs tTLHs tSET tHOLD PARAMETER Propagation delay SDA to SDAn or SCL to SCLn Propagation delay SDA to SDAn or SCL to SCLn Propagation delay EXPSDA1 to SDA or EXPSCL1 to SCL Propagation delay EXPSDA1 to SDA or EXPSCL1 to SCL Propagation delay EXPSDA2 to SDA or EXPSCL2 to SCL Transition time, SDA/SCL Transition time, SDA/SCL Enable to Start condition Enable after Stop condition TEST CONDITIONS Waveform 1; Note 2 Waveform 1; Note 3 Waveform 1 Waveform 1 Waveform 1 Waveform 1 Waveform 1 LIMITS3 MIN 105 110 109 130 160 58 -- 300 300 TYP 202 259 193 153 234 110 0.85 RC -- -- MAX 389 265 327 179 279 187 -- -- -- UNIT ns ns ns ns ns ns ns ns ns NOTES: 1. The SDA and SCL propagation delays are dominated by rise times or fall times. The fall times are mostly internally controlled and are only sensitive to load capacitance. The rise times are RC time constant controlled and therefor a specific nmerical value can only be given for fixed RC time constants. 2. The SDA high to low propagation delay, tPLHs, includes the fall time from VCC to 0.5 VCC of the EXPSDA1 or EXPSCL1 pins and the SDA or SCL fall time from the quisent high (usually VCC) to below 0.3 VCC. The SDA and SCL outputs have edge rate control circuits included which make the fall time almost independent of load capacitance. 3. The SDA or SCL low to high propagation delay includes the rise time constant from the quisent low to 0.5 VCC for the EXPSDA1 or EXPSCL2, the rise time constant for the quisent low to 0.5 VCC for the EXPSDA1 or EXPSCL1, and the rise time constant from the quisent external driven low to 0.7 VCC for the SDA or SCL output. All of these rise times are RC time constants determined by the external R and total C for the various nodes. AC WAVEFORMS INPUT SDA OR SCL 0.7 VCC tTHLs tTLHs 0.7 VCC 0.3 VCC 0.4 V tPHLs EXPSDA1 OR EXPSCL1 0.5 VCC EXPSDA2 OR EXPSCL2 0.5 VCC 0.5 VCC tPLHE1s tPHLs tTHLs OUTPUT SDA OR SCL 0.7 VCC 0.3 VCC 0.52 V 0.3 VCC 0.7 VCC tPLHE2s tPLHs tPLHs 0.3 VCC 0.4 V EFFECTIVE STRETCH TEST CIRCUIT VCC VCC VIN PULSE GENERATOR RT VOUT D.U.T. RL CL 0.5 VCC Test Circuit for Open Drain Outputs DEFINITIONS RL = CL = RT = Load resistor; 1.1 k for I 2C and 500 for EXP. Load capacitance includes jig and probe capacitance; 100 pF for I 2C and 100 pF for EXP Termination resistance should be equal to ZOUT of pulse generators. SW01088 SW01089 Waveform 1. 2002 Aug 20 8 Philips Semiconductors Product data Expandable 5-channel I2C hub PCA9518 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 2002 Aug 20 9 Philips Semiconductors Product data Expandable 5-channel I2C hub PCA9518 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 2002 Aug 20 10 Philips Semiconductors Product data Expandable 5-channel I2C hub PCA9518 Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specifications defined by Philips. This specification can be ordered using the code 9398 393 40011. Data sheet status Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. Product data Production [1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2002 All rights reserved. Printed in U.S.A. Date of release: 08-02 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. Document order number: 9397 750 10258 Philips Semiconductors 2002 Aug 20 11 |
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